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Digital Modeling Yields Efficient Rigid-Flex PCB Design Processes

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More than ever before, product experiences are being driven by customer interaction (i.e., seeing, touching) with the physical, mechanical model. The necessity to constantly satisfy the senses of the physical experience requires that printed-circuit-board (PCB) assemblies be smaller and denser to fit pre-conceptualized mechanical structures.

The mechanical model becoming such an influential factor has turned flexible electronics into an increasingly common, and significant, design objective. To gain this flexibility, designers often opt for rigid-flex PCBs, which combine both the rigid and flexible substrates of a PCB into a single design element.

Despite its numerous benefits, rigid-flex PCB design presents significant challenges in terms of effective, efficient execution. Among the many variables that go into the rigid-flex PCB design process, the greatest challenge faced by designers is ensuring that all flexible sections on the PCB fold in the correct way, while maintaining flex-circuit stability and product lifespan at the highest feasible degree of quality.

So how do you go about ensuring that your rigid-flex PCB folds as desired while fitting precisely into an existing mechanical enclosure? Let’s explore some of the current practices.

Child’s Play—The Paper Doll Approach

The most common method deployed by design teams to ensure that a rigid-flex PCB design will fit in an enclosure is the “paper doll” model of the PCB. These models, created from paper, are cut into what’s hoped to be an exact shape of the PCB in concept. This method has its roots in traditional PCB applications, but recently gained widespread use with the need to model flexible circuitry. Most PCB fabricators still promote this approach.

Figure 1 shows an example of a cardboard paper doll being used to model the mechanical fit of a stepper-motor controller. To create this model, the designer first made a 1:1 printout of the 2D PCB outline, then cut it into its final shape. To more accurately model the assembly and provide a more precise feel to the model, the designer glued a piece of cardboard to the paper model to approximate the thickness of the rigid parts of the PCB.

1. To make this paper doll a rigid-flex PCB for a stepper-motor controller, the designer printed a 1:1 copy and then cut out the final shape.

While effective at modeling an approximate shape of a rigid-flex PCB, the paper doll approach has a number of inefficiencies and problems in application, including:

Imprecise thickness: The paper doll isn’t the same thickness as the rigid and flexible sections of the PCB. Therefore, it becomes very difficult to simulate the bending of the paper model because it will bend in its final application. This makes it incredibly challenging to get a clear idea about the fatigue or natural folding properties of the design.

No 3D models: The paper doll doesn’t include all of the 3D component models that will appear in the final design. One must wonder how the presence of these models will change how the model folds, and whether a 3D model might interfere with the clearance required for the rigid-flex sections to fold properly.

Costly 3D printing: To determine a correct board fit with an enclosure, it might be necessary to print the enclosure with a 3D printer. Depending on the complexity of a design, this can become a costly option to implement—it adds a layer of unnecessary expenses to a project that could have been simulated entirely in software.

Despite its widespread use, the application of paper doll models to simulate the real-world application of a rigid-flex PCB design is both imprecise and impractical. Designers who rely on this method to ensure a correct PCB fit with the mechanical enclosure risk the potential of design revisions and expensive prototype adjustments during the fabrication process. So, are more sensible and efficient approaches available to designers?

Digital-Modeling Efficiencies

Rather than build an inaccurate paper doll model, a more sensible approach is to handle all of the modeling and simulations directly in the digital software environment. Not only will this approach save time and money, it will also yield a more exact design that doesn’t depend on the imprecision of paper models.

In practice, there are currently two accepted methods to execute this approach: using a combination of mechanical computer-aided design (MCAD) tools and electronic computer-aided design (ECAD) tools, or using an ECAD tool alone with built-in 3D functionality.

MCAD/ECAD Modeling

This is commonly referred as the “sheet-metal method” because of its inherent similarity to designing a sheet-metal part. While relatively straightforward, one must be cognizant of the number of steps involved in this process.

The initial MCAD model of the product is designed alongside a sheet-metal component, which forms part of the assembly. Once the MCAD model is created, one or more fixed tabs model the rigid sections of the design, and stiffener is used for the flexible portions.

This method offers a precise, organized way to discover what area is available for the PCB substrate. However, this shape still must get into the PCB designer’s workspace. To complete the final steps in this process, you could use the “unbend” and “unfold” features in your MCAD environment to generate the necessary models. These could then be imported to your chosen PCB editor.

The generated data, which can be exported to a PCB editor as an IDF or DXF file, will provide the outline of the rigid-flex section of the PCB for further refinement in the ECAD environment. Once in the PCB editor, components are placed and an IDF file is generated again. Then the file is imported back to the MCAD environment, where the mechanical designer can refold the board substrate.

The process of positioning the board and components as a folder circuit is time-consuming, though, rendering this approach somewhat unidirectional from MCAD to ECAD. As a result, it may still be iterative and require close cooperation between MCAD and ECAD designers.

2. This flattened “sheet-metal” shape can be exported to an ECAD environment as the PCB outline.

Figure 2 shows this in practice, with the rigid-flex PCB of our stepper-motor controller being modeled in the MCAD environments. The neon-blue highlighted sections are the “unbended” sheet-metal sections (representing the flattened flex-circuits). This unbended model is exported as DXF to the PCB design tool.

While the MCAD/ECAD translation process provides a more exact replication of a rigid-flex PCB, it does require the tedious process of translating design data back and forth between each design environment. What if you only had to use one design environment to accurately model and simulate your rigid-flex design?

ECAD Modeling with 3D

A more efficient way to design a rigid-flex PCB is to use an ECAD tool with 3D functionality. With 3D functionality built into the ECAD environment, designing a rigid-flex PCB requires fewer steps from design to completion, greatly reducing the amount of time invested in a design.

When using an ECAD tool with 3D functionality, the PCB layout and mechanical assembly are modeled together with the use of 3D STEP models. This allows designers to easily visualize the entire assembly, including the necessary mechanical enclosure and component models.

This process isn’t intended to replace a dedicated MCAD system. Rather, it’s a major step forward in improving workflows and lessening the time wasted modeling and simulating a completed product design. The ability to model both the PCB and associated mechanical enclosures and components provides designers with a high degree of precision when checking mechanical clearances in real-time 3D, ensuring that a board fits right the first time.

In addition to the above mechanical modeling capabilities, the use of ECAD software with 3D functionality provides access to the PCB’s dielectric and copper information. When utilizing this information in an MCAD environment, the mechanical designer has access to more detailed simulation options, including thermal and electromagnetic analysis.

3. Shown is a typical workflow using ECAD software with 3D functionality. After generating the PCB outline, the electrical designer can define the needed layer stacks for the rigid and flexible sections of the PCB, and then assign these layers to appropriate areas on the design.

Figure 3 illustrates a typical workflow using ECAD software with 3D functionality. Once the PCB outline is generated, the electrical designer can define the needed layer stacks for the rigid and flexible sections of the PCB, and then assign these layers to appropriate areas on the design.

After completing this step, the bending and folding areas of the final product are defined, and can be examined and simulated in detail to ensure correct form. At this stage of the design process, it’s easy to verify if the flexible portions of a design are too short or long and adjust them accordingly.

Once the modeling process is complete for both the rigid and flexible parts of the PCB design, engineers can then place the needed components on the board, including connectors, heat sinks, LEDs, light pipes, and other mechanical models. During this process, it’s beneficial to have a STEP model of the final enclosure in the ECAD environment.

With this data at hand, the designer can actively check for clearances between the board, components, and enclosures all in real-time 3D, or perform a comprehensive design-rule check to identify design errors. With this integrated method, designers can expect to see a 50% reduction in the amount of time it takes to verify and validate the shape and folds of a rigid-flex PCB (Fig. 4).

4. ECAD software that incorporates 3D functionality helps streamline the process of designing rigid-flex PCBs, allowing designers to perform all necessary design-for-manufacturing (DFM) checks in the PCB design tool.

Upon completion of the modeling and simulations in the ECAD environment, designers can transfer this data back to the MCAD software as a STEP model and begin the final process of combining the PCB with the completed mechanical design.

Compounding Design Efficiencies

In addition to delivering better boards, the 3D STEP models generated from the rigid-flex design (including folded, unfolded, and partially folded states) deliver more accurate and detailed documentation. Manufacturing engineers can use this enhanced documentation to develop clear assembly instructions for both the PCB assembly and the final product.

If desired, manufacturing engineers can even produce a video from the images generated in the ECAD environment. These videos can be used to train assembly personnel in the exact process required to fold the flexible circuitry. Implementing this process helps significantly reduce assembly time and errors, thus streamlining the entire design-to-fabrication process.

Despite the benefits, it’s important to note that like any other process driven by incremental improvements in technology, not even the most precise STEP models provide a 100% accurate picture of design intent. More advanced models and systems for streamlining the rigid-flex design-collaboration process between electrical and mechanical design teams are certain to appear down the road.

Design Success Through Digital Modeling

It’s clear that maximizing the efficiencies of your rigid-flex design process goes far beyond the currently accepted methods of prototyping PCBs and enclosures with paper-based models. Ensuring that your board fits the mechanical enclosure right the first time, while also maximizing the quality of your flexible circuitry, requires a more advanced workflow incorporating the use of 3D functionality in an ECAD environment. When it comes to remaining competitive and productive, don’t leave your designs up to chance. Use a digital modeling and simulation system for the most efficient rigid-flex design process.

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Discussion on Power and Ground in Electromagnetic Compatibility of PCB

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The improving of electronic products is closely related with the progress of electronic technology. With the fast development of electronic technology, electronic products have developed towards miniature and density that brings about much interference to PCB electromagnetic compatibility design in which power and ground are the most essential part. Therefore, confronted with the development of electronic products and interference of electromagnetic design, optimization should be implemented on electromagnetic compatibility design based on the certainty of electromagnetic compatibility design interference.

Analysis on Interference of Power and Ground in Electromagnetic Compatibility

Power circuit is the media connecting electronic circuit and power grid while noise is the main reason for the interfering electromagnetic compatibility design. With the development of PCB design, voltage in electromagnetic compatibility design is also the main element leading to the instability of circuit. The interference is mainly indicated as the following aspects. First, the application of electronic components in electronic products brings about convenience to the utilization of electronic products and requires higher commands for the internal design of electronic products. Optimization is required if electronic product technology upgrading speed fails to be compatible with electromagnetic compatibility design. At this time, once the logic chips of electronic products such as DPS chip and CPU suffer from interference, the performance of electronic products will also decrease. Electromagnetic interference in PCB electromagnetic compatibility design is caused by the resistance generated by power lines and ground lines. As a result, confronted with the situation of bad electromagnetic compatibility, compatibility design of ground lines and power lines should be analyzed and optimized so that electromagnetic performance will be improved. Meanwhile, for high-speed circuits that have high current speed, they have special PCB design and fast changing current should be aligned with electromagnetic compatibility design. Moreover, when multiple circuits simultaneously apply the same power line, great interference and burden will also take place to circuits. Circuit signals are influenced as well with some limitation, too. The mutual application between circuits will lead to the generation of public impedance interference. Meanwhile, public impedance interference has more obvious effect than single line interference.

Processing Strategies of Electromagnetic Compatibility Design

• Electromagnetic compatibility design and processing of power line
As an essential part of PCB electromagnetic compatibility design, electromagnetic design and processing of power line plays a fundamental role in stabilizing PCB circuits, covering the following aspects.
First, the width of power line should be set and adjusted according to the intensity of the current passing through PCB and the scientific setting of power line width is capable of greatly reducing the current resistance in the process of loop operation.
Second, routing of power line and ground line is so important that much attention has to be paid to their routing directions. Generally speaking, the routing direction of power line and bottom line should be compatible with the flow direction of current. Nevertheless, in terms of PCB electromagnetic compatibility design, the routing direction of power line and bottom line should be compatible with the flow direction of data because the noise problem will be solved in this process.
Third, length of pins has to be set reasonably. The application of mounting components is a significant step to increase the suitability of pins. In the process of application of mounting components, it’s necessary to decrease the loop area supplied by capacitance and mounting components are capable of reducing the bad influence of distributed capacitance of components. During the procedure of electromagnetic compatibility design, the influence of component distributed capacitance is a key element leading to the generation of noise. The reason why the balance of component distributed inductance just lies in the shrinking of pin length.

• Electromagnetic compatibility design and processing of ground line
Electromagnetic compatibility design and processing of ground line is mainly to decrease the interference of ground loop and eliminate the bad influence of noise on PCB electromagnetic compatibility, which can be implemented from the following aspects.
First, the formation of loop current is the key cause of ground loop interference. However, to practically reduce the formation of loop current, the first job is to design ground line in terms of its electromagnetic compatibility. Specifically, the application of isolator and common mode choke is right the essential measure to decrease loop current. When loop current is being formed, public impedance is the major element producing effect. In order to avoid the conflict between loop current and loop ground line design, a layer of thick ground lines are required to be paved adjacent to ground loop to stop the formation of loop current that causes noise interference. Moreover, the accuracy of extreme position should be ensured. For ground line plane in a multi-layer PCB, specific setting has to be carried out. Meanwhile, in the process of PCB electromagnetic compatibility design, adjusting the assembling of shifter is actually an important measure to adjust noise interference, which means that adjustment on shifter is capable of reducing noise when noise interference goes beyond certain limit.
Second, the resistance of public part is the main element leading to electromagnetic compatibility design interference. Nevertheless, for the smooth implementation of electromagnetic compatibility design of ground line, the electromagnetic compatibility design of public part is the most important job and either thickening ground line or coating processing is capable of avoiding the resistance of public part. Therefore, the change of ground mode is capable of processing and optimizing parallel single point. Meanwhile, in the process of series and parallel design, the generation of single-point ground can also eliminate public resistance as much as possible.
Third, digital ground and analog ground should be independent from each other. On the one hand, digital ground and analog ground should be independent from each other; on the other hand, digital ground should be designed independently and analog ground has to be ensured to fail to interfere with digital ground. In the process of parallel and series mutual ground, single-point grounding is the commonest mode that fails to reduce interference as much as possible to stop from interference led by circuit with low frequency. Therefore, circuit with high frequency should be connected with series and parallel circuit.

• Hazardous substance detection
Hazardous substance detection for electronic products mainly consists of application of detection method, determination of detection projects and recycling of discarded exported electronic products.
a. Sample quantity and selection of method for hazardous substance detection for electronic products.
b. Determination of detection items. Similar with commodities in the market, raw material for electronic products has different quality and types. The raw material should be determined according to the specific environmental protection project by electronic product suppliers and manufacturers, which also benefits the improvement of detected result. Detection should be implemented from the following aspects.
First, the type, quantity and indexes of electronic products should be ensured to reach corresponding standard coupled with features of manufacturing procedure craft.
Second, it is a key point to detect from all positions and angles. Legal and authoritative detection has to be implemented so that the detected result is both complete and accurate.
Third, physical and chemical features have to be fully understood to reduce the influence of detected environment on electronic products to the minimum and reduce measurement error. Electronic products with different properties are required to correspond to different detection grades so that detected data can be more accurate and scientific.
c. The recycling and destruction of discarded electronic products.
After detection, discarded electronic products are required to be recycled in time that are incompatible with standard and do harm to people’s health. If necessary, discarded electronic products have to be destroyed to avoid bad influence.

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Commonly Seen PCB Design Issues

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The most basic form of design for manufacture as it applies to PCBs is the use design rules and design rule checking in PCB design software. Design rule checking (DRC) is the process of looking at a design to see if it conforms to the manufacturing capabilities of a PCB fabricator. Typically the designer will get the highest tolerances that a PCB fabricator supports from the fabricator, load these tolerances into their design program and then run a design rule test on their prospective design. Design rule checks are commonly integrated into PCB design software and are not typically considered as add on service. More advanced design for manufacture analysis software is also available to look for more complex and less obvious design flaws. Typically, DFM software checking is offered by PCB fabricators to customers as an extra service. The reason for this distinction is because of the plus cost of high end DFM software and the additional training required for using it.

Common DFM issues

1. Starved thermals

Starved thermals occur when the thermal relief traces connected to a pad are not properly connected to the associated copper plane. Quite often, the spacing between vias will pass a basic design rule check, but the attached thermal relief traces will be interrupted and the effected vias will be inappropriately isolated from their assigned copper pours. This issue is most commonly seen when multiple vias are placed in proximity to each other.

2. Acid traps

When two traces are joined at a highly acute angle it is possible that the etching solution used to remove copper from the blank board will get “trapped” at these junctions. This trap is commonly referred to as an acid trap. Acid traps can cause traces to become disconnected from their assigned nets and leave these traces open circuited. The issue of Acid traps has been reduced in recent years by fabricators switching to the use of photo activated etching solutions. So, while it is still a good idea to make sure that your traces do not meet acute angles, the issue is less of a worry than it had been in the past.

3. Silvers

If very small portions of a copper pour are only connected to larger portions of the same copper pour through a narrow trace, it is possible for them to break off during fabrication, “float” to other parts of the board and cause unintended shorts. The problems presented by silvers have been reduced in recent years by fabricators switching to the use of photo activated etching solutions. So while silvers are still to be avoided in designs, they are not as predominate of an issue as in the past.

4. Insufficient annular ring

Vias are made by drilling through pads on either side of a board and plating the walls of these holes to connect the two sides of the board. If the pad size called out in the design is too small, the via may fail due to the drill hole taking up too large of a portion of the pads. Minimum annular ring size is commonly part of the DRC process. This issue is mentioned here because of the not uncommon occurrence of missed drill hits in prototyping boards.

5. Via in Pads

Occasionally it may be convenient to design via to be positioned within a PCB pad. The designer should note that via in pads can cause issues when the time comes for the board to be assembled. Via will draw solder away from the pad and cause the component associated with the pad to be improperly mounted. The image below shows difference between via in pad PCB and normal PCB.

Via in Pads sample_PCBCART

6. Copper too close to board edge

Normally caught during design rule checks, placing copper layers too close to the edge of a board can cause those layers to short together when the board is cut to size during the fabrication process. While this sort of error should be caught using DRC features typically available in PCB design software, a PCB fabricator that does a DFM check will also catch this issue.

7. Missing solder mask between pads

In very tightly spaced, small pin pitch devices, it is quite common for there to be no solder mask between pins due to standard design settings. The omission of said solder mask can lead to solder bridges forming more easily when the fine pin pitched component is attached to the PCB during assembly.

PCBCART has been providing professional PCB assembly services for years, we are capable to refrain from missing solder mask between pads. The image below shows our high precise solder mask between 0.4 pitch QFN pads.

Missing solder mask between pads sample_PCBCART

8. Tombstoning

When small passive surface mount components are soldered to a PCB assembly using a reflow process, it is common for them to lift up on one end and “tomb stone”. Tombstoning can greatly affect PCB yields and quickly drive up production costs. The source of tombstoning can be incorrect landing patters and imbalanced thermal relief to the pads of the device. Tombstoning can be effectively mitigated by the use of DFM checks. Below image is a tombstoning sample and its schematic.

Tombstoning and its schematic_PCBCART

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The PCB Manufacturing Process

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PCBs are the basis of all electronics designs. They allow complex designs to be manufactured in a reliable and repeatable way. While the manufacture of PCBs is typically handled by a PCB fabricator, it is important for PCB designers to understand the manufacturing process. With an understanding of the process a designer has an insight into some of the opportunities for errors to be introduced into their PCB designs and how to avoid them. Furthermore, PCB designers can also benefit from understanding all of the capabilities of modern PCB fabricators and take advantage of these capabilities when tackling their next PCB based application.

Broadly, this article will discuss how a PCB goes from being output by PCB design software to being manufactured into a physical PCB by a PCB fabricator. As an initial point of reference, let us first look at a diagram of a four layered PCB board:

PCB Manufacturing Process_PCBCART

Starting from the center of our four layered board PCB diagram and proceeding out: The PCB is based on a fiberglass substrate, with copper layers stacked on top of the substrate and further copper layers separated by additional layers of substrate. Finally, the board is terminated on both sides in a solder mask layer. The substrate provides the PCB with mechanical stability, the copper layer functions as the conductive portion of the board and the solder mask protects the copper from shorting to the outside environment. Additionally, vias are used to connect copper traces from different layers of the design. The solder mask is also typically marked with informative marking on a layer that is called the silkscreen. Markings on the silkscreen include the names and references of components as well as information about the board revision and manufacturer.

With the general description of a multilayer PCB board in hand, we can continue to discussing how a PCB is taken from its basic components and made into a final product:

1.Design Files are Sent to a Fabricator

Once PCB design files have been submitted to a PCB fabricator, the first step in the PCB manufacturing process is running a design rule check on these design files. Commonly called Design for Manufacture (DFM) check, when a design is received by a PCB fabricator from a customer, the fabricator will check the design files to see if they conform to the minimum tolerances of his manufacturing process. Some common checks include checking a design for minimum trace width, trace spacing, minimum drill hole sizes and board edge spacing. The file standard for designs is extended Gerber, which is an industry standard file format for the description of PCBs. Almost all PCB design software is capable of producing Gerber Files, so they can be sent to the fabrication houses the designer chooses for manufacture.

2.Turn PCB Design Files into Photo Films

Once the PCB design files have been confirmed they are then sent to a plotter, which is essentially a specialty laser printer, to generate photo-films. Photo-films start as clear plastic sheets. The plotters then print the PCB designs onto the photo-films with black ink. When completed, the photo-films for the inner layers of the PCB are essentially negatives of the PCB design, where the portion of the design that is going to be copper is black and the portion that is not conducting is clear. The Photo-films used on the outer layers of the PCB are the opposite. On the Photo-films for the outer layers the board the layer where copper is to remain is clear and the portion where copper is to be removed is black. Photo films are made for each layer of the PCB design and the solder mask, so a design of two layers would have four layers of photo-films printed, a four layer design would have six printed and so forth. The last step in the production of the photo-films is to punch them so that they can be precisely aligned in later steps of the PCB manufacturing process.

3.Printing Designs on the Copper Clad Substrate (Inner layers)

This step (along with 4, 5 and 6) is only completed when we have more than a two layer board. In the event that we are manufacturing a two layer board we would skip to step 7 (drilling).

With the photo films in hand, we can now turn our attention to the substrate and base copper layers of the PCB board that is going to be produced. Blank copper clad fiberglass boards are the basis of the vast majority of PCB designs. These copper clad panels are initially cleaned and then coated with a photo resist layer. The photo resist layer is a layer of photo reactive chemicals that harden when exposed to ultra violet light. Once the photo resist layer has been installed on the copper clad substrates, the photo films are placed onto the board and the board is exposed to an ultra violet light source. The portions of the photo film that are opaque prevent the photo resist layer from hardening, while the clear portions allow for the resist to harden. After the ultra violet light exposure portion of the process is complete, the photo films are removed from the board and then the board is washed with an alkaline solution to remove the unhardened photo resist. What is left at the end of this process is a copper clad board with resist over the portions of the board that are to remain copper in the final design.

4.Etching Inner Layer Copper

Once we have the resist layer printed on the copper, we can now proceed to remove the unwanted copper portion of the board. This is done by exposing the copper board with resist to powerful copper solvent solutions which remove all of the copper from the fiber glass substrate that was not covered in resist during the previous step. It is of note that different weights of copper require different amounts of exposure to copper solvents, which in turn, can indicate different track spacing requirements. With the unwanted copper removed, the resist that protected the desired copper can now be removed. The result is the substrate with the desired copper layer or layers.

5.Inner Layer Registration and Optical Inspection

Once the substrate with inner layers has been produced, the resulting product is given alignment punches to allow it to be aligned to other layers in the process correctly. The copper layers in the resulting process can also be inspected for correctness at this point. This sort of inspection is typically done using an optical inspection system, which compares the original design files to the actual copper traces produced by the etching process.

6.Lay-up and Bonding of Outer Layer

At this point, if your design has more than two layers, additional layers must be bonded to the substrate. This is done by laying what is called prepreg (short for pre-impregnated) and a copper foil on the top and bottom of the original substrate, with it’s now etched copper traces. Prepreg is essentially fiber glass with epoxy impregnated into its structure. The substrate/prepreg/copper stack up must now be bonded together. This is done by placing layers in a metal clamp and heating them while they are under pressure. This is typically achieved in specialty bonding presses, which can heat and cool the layers in the correct fashion as they press the layers together, to insure that they are well bonded.

7.Drilling the PCB

Once we have the blank outer layers of the PCB in place, we can proceed with drilling out all of the required holes in the PCB design. The drilling is done with a computer controlled drilling machine. The drilling machine takes the drilling file from the submitted design files and places drill holes accordingly. The copper stack up is placed in the drilling machine and aligned to insure that the drill holes are properly placed. Entry and exit material is used to insure that the drill holes do not mare the copper during the drilling process. Finally, excess copper is cut off from the edges of the production panel using a profiling tool. The drill holes from this step in the manufacturing process will become the vias and mechanical mounting holes of the design, once they are plated later in the process.

8.Copper Deposition

With the drill holes in place in our panel, we now proceed in plating these holes to connect the different layers of the design together. This plating process is done via a chemical deposition process. The drilled panel is cleaned and then dipped into a series of chemical baths, which results in a very thin layer of copper being plated on all of the holes of the design and coincidentally the outer layer of copper of the panel.

9.Image the Outer Layers

The next step in the process is imaging of the outer layers of the copper stack-up. Once again a layer of photo resist is applied to the outer copper on the panel. The photo films with the outer layers of the design printed on them are then used to preferentially expose portions of the PCB where copper will not remain to ultra violet light. This is the opposite of the inner layers, where the portion of the board that is exposed is the portion that will not remain. The result is the board with resist covering all the areas that will eventually be removed.


Now the board will go through the electro-plating process. As the board now stands, the exposed portions of the board are the portions of the board that were left exposed in our last step and the previously chemically plated copper through holes. Once the initial copper electro-plating is complete then the board is typically plated with tin. This will allow for the removal of all of the unwanted copper that is still remaining on the board, while the tin protects the portion of the board that we want to remain during the final copper removal process.

11.Final Etching

Our board now has a layer of resist along with the tin plated copper traces that we want to remain. The next step in the process is to remove the resist layer and finally the unwanted copper that is left under the resist. This is done by a chemical process which removes the exposed copper, but does not remove the tin plated portion of the outer layers. At the end of this step we have all of our conducting areas and connections in place.

12.Apply Solder Mask

The next step in the process is to apply a layer of solder mask to each side of the board. Panels must first be cleaned and then coated with an epoxy solder mask ink. The boards are then once again exposed to UV light through a solder mask Photo Film. The portions of the board that are not exposed to UV light are left soft and are therefore able to be chemically removed later in the process. Once the unwanted solder mask has been removed the PCB is further cured in an oven to insure the solder mask stays intact for the life of the PCB.


Now that we have the tin finished exposed copper pads, we further plate the exposed PCB pads for solder-ability. Commonly PCBs are chemically plated with Gold or Silver. PCBs can also be supplied with the pads having undergone a hot air leveling process. The hot air leveling uses hot air to insure that the pads are all manufactured to a highly similar and precise depth.


Now that the board is largely complete it is time to apply a silk screen layer to the board. The silk screen indicates which components go where during assembly and how they are oriented. While this layer is commonly referred to as the silk screen layer, it is no longer commonly implemented using a silkscreen. Rather, it is typically printed directly onto the PCB using an ink-jet type process. Once the silkscreen has been placed on the board, the board goes through a final coating and curing process.

15.Electrical Test

With a complete board in hand, the board can be electrically tested. This is typically done through an automated process in which the integrity of the different nets of the design is tested. This is automated, by having the original design file define the location of the nets to be tested and then having a “flying-probe” test that the different nets of the design are in fact isolated.

16.Profiling and V Scoring

The last step in the manufacturing process is mechanically cutting out the different boards housed in the original panel. This can be done with a router which leaves small tabs along the board edges or with a v-groove which cuts diagonal channels along both sides of the board. Both approaches allow for the individual units of the boards to be snapped out of the panel manually. Quite often the boards will remain in a panel all the way through assembly.


Hopefully this article help illuminate the PCB manufacturing process. While the details of the process can change somewhat from manufacturer to manufacturer, the process used will closely resemble that outlined above.

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Possible Problems and Solutions in the Process of PCB Design

Category : Uncategorized

Compared with the development of software system, the hardware design and its optimization of electronics have seen the practical problems such as long time consumption and high cost. However, in the actual design, engineers tend to pay more attention to the highly principled issues but what lead to the great influence on the operation of printed circuit boards is just some detailed errors that we have to correct over and over. It’s impossible for the perfect generation of PCBs but gradual optimization can be obtained. This passage will first list some problems on circuit design, PCB production and maintenance and then provide some easy to use methods to optimize custom PCB within limited cost.

Withstand Voltage Protection of Multi-Channel Power Rectification LED

Take a corridor public electricity equipartition as an example. In order to ensure the normal operation of the circuit, multi-channel power is utilized to provide electricity to power module that is AC-DC module with the parameters “Uin=AC85~264V”. IN4007 rectification LED that is series with 300?1/2W carbon resistor is utilized by multi-channel input for isolation. Figure 1 is the circuit diagram of this product.

Theoretically, it is a perfect idea while there are serious problems in the actual use. Without spike voltage considered, in the normal situations, the voltage between multi-channel power can reach AC400V and the withstand voltage of IN4007 can reach 1000V. The right components are picked up, right? But the fact is that the short cut blast often happens because of the withstand voltage problem, leading to the scrap of the whole product. Of course, it can’t be denied that the low quality of components and the aging of LEDs also contribute to the problem. But even if high-quality LEDs or LEDs with higher withstand voltage are installed instead of previous ones, the problem still stands there.

Considering the quality problems of early fatigue within warranty and the existence of throughput yield (TPY), it is nearly impossible for components to reach 100% TPY. As to this circuit, 24 rectification LEDs are required in this advanced circuit with the scrap rate range from 2.4% to 7.2%. PCBs with such a quality are never capable of fully realizing customers’ needs. As a matter of fact, here is an easy to use way to handle this problem. As long as one more IN4007 is placed series in each loop, this problem will be easily dealt with. Because at this time, the circuit voltage is reduced by 0.7V, it has no effect to output. Only a little increase of cost brings about the double withstand voltage values and a decrease of error occurrence to 0.5%.

Solutions to Electromagnetic Interference by the Frequent Operation of Midget Relay

The electromagnetic interference brought by the midget relays on PCBs since arc discharge will be produced when they are cutting high current. The interference not only influences the normal operation of CPU, leading to frequent reset, but makes decoders and drivers produce wrong signals and instructions that result in the error of component implementation as well. All these influences will cause defective goods and accidents. In order to solve this problem, two aspects can be considered: increasing the anti-interference capability of CPU and reducing the interference source.

1. Increase the anti-interference capability of CPU

A CPU with high anti-interference capability must be installed. The selection of CPUs also need experiments and test. For example, 90C52RC SCM is an ideal selection. This type of CPU features 20KV anti-static capability and 4KV anti-fast pulse and electromagnetic capability.

2. Reduce the interference source

  • • Relay-driven amplifiers are capable of effectively reducing the interference generated by back electromotive force when coil is in an outage.
  • • RC absorption circuit is connected parallel between relay contacts so that noise interference can be rapidly absorbed.
  • • Circuit boards are copper clad. Copper clad is greatly helpful in reducing the relay interference.
  • • Relays must be carefully selected. Relays with the same specification always have selections of different coil power. The basic principle is that the larger the coil power is, the more quickly the relay contact on-off actions become, the shorter the time of arc discharge between contacts is, the shorter the electromagnetic interference time becomes.

The Improvement of Pad Off

Neither disassembly nor soldering can be avoided when PCBs are under maintenance. The aging PCBs or PCBs with too small pads always witness the pad off and soldering layer off on plate hole wall when components are disassembled from PCBs.

1. As to the pin pad off, the nearby pad on the same route can be connected to it with a short line that can be selected according to the distance and the amount of current it can hold. For the short distance, the trimmed discarded pins or pin header can be used for soldering; for the long distance, copper wires with outside insulating layer can be used for connection in order to avoid the short cut caused by the connection between lines and pins of other components. When pad off problem always takes place in this place, it can be verified that the PCB design here is so irrational that the design of pads must be optimized. Pads can be designed into long-round or water drop shape within the usable space and short and thick copper clad lines can be added to increase its absorption capacity towards PCB material.

2. As to the soldering layer off on plate hole wall, the reason lies in the small size of the plate hole. When components are disassembled from PCBs, comes along with the soldering layer of plate hole wall. So it’s suggested that the size of pad hole should be 0.3 to 0.5mm larger than that of pins in the process of design. When soldering tin layer on the pad hole wall has been fallen off, this method can be tried. Pins of new components should be installed before tin coating with the soldering tin layer a little thicker. Next is the pin soldering. The soldering tin layer on the pin is capable of soldering the pads on PCBs easily.

Replacement of Vulnerable Components

As long as the electronic components are used, some parts become vulnerable and need to be changed or replaced. The usual method of maintaining these components is through soldering that leads to much time consumption, strongly influencing the work efficiency. It is suggested that bases are added to vulnerable components or connections can be made through plugs or insert rows. This method helps engineers save a lot of time and effort.

PCB design and optimization is a complicated process, requiring both a design blueprint and trivial details. Optimizing each detail leads to time consumption and cost decrease in PCB manufacturing process.


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EMI and Signal Integrity: How to Address Both in PCB Design

Category : Uncategorized


toc_F1_shutterstock_170100419Let’s do a comparison of EMI (electromagnetic interference) design and signal integrity. EMI focuses on the associated specifications and testing requirements and interference between neighboring equipment. Signal integrity addresses the degradation of signal quality to the point where erroneous results occur. But the overlap in design techniques at the board level is considerable. Note that the IEEE EMC Society has a subcommittee devoted to signal and power integrity.

We consider signal integrity to be EMI at the circuit board level. Our experience is that a circuit board that is well designed for signal integrity is generally pretty good for EMC as well. Let’s take a closer look at these issues, and see where they differ and where they overlap.

Different Focus, Similar Techniques

With signal integrity, the focus is on printed circuit board and associated interconnections between circuit boards. The objective is clean signals along with adequate operating margins (timing, supply voltage, and environmental variations). This has become a major factor with the increasing serial I/O speeds, headed to 100 GHz. The key concerns are signal reflections, crosstalk, ground bounce and power decoupling. The solutions are careful circuit layout and attention to timing. The interference levels of interest are millivolts and milliamps.

EMC focuses on the entire system, including printed circuit boards, enclosures and cables and power supply. The objective is to pass relevant EMC test requirements and to make sure it works in its intended application. The key concerns are emissions, immunity, and mutual compatibility of equipment, including digital and analog circuits, motor controls, relays, etc. The remedial solutions are careful circuit layout, grounding and shielding, filters and transient protection. The relevant signal levels are microvolts and microamps for emissions, and kilovolts and amps for immunity.

The common area is at the circuit board and local interconnect area. Even here, there are some clearly different aspects of interest. First, note that the key signal levels of concern are very different. For signal integrity, the key factor is to keep noise levels substantially below the signal levels, so our noise margins are in the millivolt range for digital circuits. But, for EMI, emission levels must be kept in the microvolt and microamp range, typically three orders of magnitude lower than acceptable internal noise levels. For immunity, external levels may well be in the kilovolt and amp range, again, orders of magnitude higher than logic levels and analog circuit levels.

This means that parameters entirely acceptable with signal integrity can be grossly higher than that needed for emissions and grossly lower than needed for immunity.

Parasitic coupling paths are more critical for EMI, but signal losses are more critical for signal integrity.

Let’s see how these factors affect board design.

Ground Impedance

Ground impedance is at the root of virtually all signal integrity and EMI problems; low ground impedance is mandatory for both. This is readily achieved with a continuous ground plane, and exceedingly difficult with traces, as would be used in a two layer board. We’ll deal with multilayer boards, where it is feasible to implement a ground plane.

Ground impedance is an important issue for both signal integrity and especially for high frequency emissions in EMI. A ground plane serves well as a signal return, provided the ground is continuous under the signal path. But, even with a continuous return path, there will be enough voltage drop across ground to generate a common mode voltage. This is not significant for signal integrity, but is the primary cause of common mode voltages which, left unchecked, will escape as an EMI emitter via the signal or power ground conductor.

Here, we note that common mode currents are purely parasitic. They contribute nothing to the desired signal but can be difficult to block as EMI emitters. Differential mode currents are the normal signal path, and are more of an issue with signal integrity than with EMI. These considerations are driven by the loop area; inductive impedance of the signal/return loop is proportional to the loop area, as is the antenna efficiency (a consideration for radiated emissions and immunity). But signal/ground loop areas on a multilayer circuit board are small, providing the return path in ground is continuous, and is usually not a problem with EMI.

Copper thickness is not an important factor. At high frequencies, skin effect dominates, so currents are squeezed to the surface, rendering extra thickness irrelevant.

In fact, the principal problem with ground impedance is the discontinuities that occur in the signal return path, and that has major impact on characteristic impedance control.

Impedance Control

At higher frequencies, characteristic impedance control becomes necessary for signal integrity and, to a lesser extent, for EMI control. Now we are operating well into the GHz range, and impedance control requires meticulous care just to maintain signal integrity. For EMI, it is usually sufficient to minimize overshoot and undershoot, especially with signals leaving the circuit board.

The biggest problem with maintaining impedance control is the signal path discontinuities, including return path on ground plane:

1. The ideal signal path has a continuous copper plane immediately underneath. In such a case, impedance control is confined to proper terminations, usually at the load end. For slower signals, where EMI control is the predominant issue, source termination is often an appropriate choice, as it also limits the emission currents from leaving the driver chip. Source termination does slow the signal, which may not be acceptable for highest speeds.

2. The worst discontinuity occurs if the signal changes reference planes from a ground plane to a voltage plane, as illustrated in Figure 1. Clearly, ground to voltage vias can’t used to provide a return path, so the only option is to insert decoupling capacitors at the perimeter in order to provide a low impedance high frequency return path across the boundary. Unfortunately, this is not a fully acceptable solution at high frequencies, but will be reasonably good for lower frequency signal paths.

Figure 1: Return current path is discontinuous when switching reference planes

Figure 1: Return current path is discontinuous when switching reference planes

3. A lesser discontinuity occurs if the signal is transitioning from one ground plane to another. Here, the return path from plane to plane must be made continuous and impedance control effected. Typically, this is handled by inserting ground to ground vias around the perimeter of the signal via, and controlling the keepout, pad size and via size and length in order to match impedances.

4. The least problem of layer changing occurs when the signal transitions from one side of the ground plane to the other (see Figure 2). Since we haven’t changed reference planes, there is no issue with ground vias, so the impedance discontinuity is minimal. For highest speed signal integrity, you will need to minimize the impedance discontinuity by controlling the via size and length, and the diameter of the keepout.

Figure 2: Return current past discontinuity is minimized when keeping same reference plane

Figure 2: Return current past discontinuity is minimized when keeping same reference plane

5. Cuts in plane, as shown in Figure 3, shows a discontinuity in the signal return current path. The return path has to go around the gap in the plane, raising the characteristic impedance at the gap, and energizing the opening as a slot antenna. This can occur when a portion of the plane is stolen to accommodate another trace, at a split plane boundary, or at a connector cutout.

Figure 3: Signal return path is disrupted by cut in ground plane

Figure 3: Signal return path is disrupted by cut in ground plane

6. Signal path at mandatory discontinuities. This assumes that impedance control needs to be maintained across the boundary. Most notably, this will occur at the circuit board to connector boundary (see Figure 4), and is especially noticeable when the impedance of the cable doesn’t match the impedance at the circuit board. In such a case, an impedance matching network needs to be placed at the boundary. This is handled by controlling the copper parameters at the boundary. Larger cutouts increase inductance while leaving more copper at the boundary increases capacitance.

Figure 4: PCB to coax impedance matching

Figure 4: PCB to coax impedance matching

PCB Layout

For both EMI and signal integrity, good layout starts by identifying critical traces. In both cases, most of the problems lie with a very few of the traces. You don’t have the time or real estate to treat all the traces, so you concentrate on the few. But the critical traces are typically different for signal integrity and EMI.

For signal integrity, the problem is limited to the relatively few high speed signal traces. High speed serial data are the leader, and design will concentrate on the signal/return path and adjacent metallic members. For EMI, the problem concentrates on those lines entering or leaving the circuit board. The primary emitters are those that carry high speed clock and data lines, along with the parasitic coupling to slower lines, power lines and especially ground lines. The primary receptors are low level analog input lines for RFI and digital lines for transients.

Once these lines are identified, you can place the chips on board to facilitate good routing. The simpler the path for critical traces, the easier it is to maintain signal integrity and EMI control.


Starting with the supply voltages, the voltage tolerances are basically a signal integrity issue. This does not show up at the EMC level except to the extent that external interference corrupts voltage at the power supply or on-board regulators. The big difference lies with the demand for decoupling. Clock noise that shows up on the power rails and sneaks out the power cable will be an emission problem even if amplitudes are in the microvolt range, but won’t be a problem for signal integrity until it reaches the millivolt range. So decoupling demands for EMI are a thousand times more demanding than for signal integrity.

The chip manufacturer recommends decoupling capacitors as needed for Vcc droop. This means that the target frequencies for signal decoupling are at the clock frequency and below, while the frequencies for emissions are at the clock harmonics, typically ten times the clock frequency or even higher.

Thus, the demands for decoupling for emissions are substantially higher than with signal integrity. This doesn’t mean more capacitance, it means less inductance. At modern computer speeds, your high frequency harmonics are inevitably operating above the series resonant frequency of the typical decoupling capacitor. Just add one to two nanohenry of lead length in each decap and you will find that the impedance is too high for effective filtering. If the impedance is above one ohm, you should look for better filtering, or more decaps in parallel. The good news is that at higher frequencies, the interlayer capacitance of multilayer boards becomes the dominant factor above a couple hundred MHz.


Crosstalk can be an issue for both signal integrity and EMI. Crosstalk is unintended coupling to adjacent metallic members, usually to an adjacent signal, power or ground path.

Crosstalk includes field coupling from one line to an adjacent line. It is a major issue with cables that will usually need to be addressed, but may also be a problem with adjacent trace coupling at the circuit board level. Any coupling from very high speed signal lines can degrade signal quality (we see signal speeds well into the GHz range, and we hear 100 GHz is just around the corner), whether to an adjacent trace or any other metallic element on the circuit board. For EMI, crosstalk becomes a problem with I/O lines coupling energy to/from clock lines or sensitive on-board lines. Often, this problem can be eliminated by separating these lines. The spacing in between need not be wasted, but can be used for less critical lines. In both cases, increased spacing is beneficial, as coupling falls off with the square of the distance.

Other Signal Path Issues

In addition to crosstalk, other losses may come into play, with series resistance and shunt dielectric loses being the major issue.

Signal path losses would include series resistance in the conductive path and shunt conductance in the dielectric. For the most part, these losses are not a problem at the circuit board level, unless you are using a high resistance signal path, such as conductive epoxy (which is rarely used). These losses become much more of a problem at the cable level, especially with signal integrity, where losses track directly with eye diagram shrinkage, to the point of signal failure. For EMI, the problem is a bit less noticeable. But obviously, if the signal strength is weakened, it takes less external interference to create data errors.

Imbalance is an extension of crosstalk, becoming increasingly significant for differential signals as serial data speeds increase. Balance loss will occur with unequal coupling paths, as mentioned above, and will also show up due to unequal propagation times from driver to receiver. This is much more of an issue with signal integrity than with EMI.

Coupling to off-board elements is primarily an EMI issue, where coupling between elements on adjacent circuit boards may be significant. A typical case is where clock noise from a high speed microprocessor chip capacitively couples to an adjacent circuit board, then propagates to the outside world from there. A similar situation occurs if an internal cable is routed too close to this same chip. This situation is increasingly being handled by on-board chip shielding. This problem rarely occurs with signal integrity issues.

Analytical Software

Let’s take a look at analytical software, clearly, a topic of significant interest.

Any modeling that reduces hardware redesign effort is like money in the bank. So what is the status?

Our observation is the modeling for signal integrity is much more developed than for EMI. It is a much simpler task to model the signal path, with consideration limited to the signal path/return, plus coupling to adjacent metallic members. The EMI predictions are much more complex, as it involves consideration of many more circuit board coupling paths and common mode noise generation, both of which are difficult to identify, much less quantify. Additionally, calculations need to consider enclosure and cable shielding effectiveness, which involves identifying all the relevant parameters and quantifying them. In actuality, almost all of the modeling is directed at emissions. (We’ve seen almost nothing on modeling of immunity issues.) The bottom line is, consider yourself as doing well if your predictions are good within 20 dB, or a factor of 10. Well, that is better than nothing, but it still leaves a lot to be done by test and redesign.


Signal integrity has become an increasingly important part of EMI design. Good circuit board design is very important in both cases, but the emphasis is different. Most notably, signal integrity is primarily concerned with the critical high speed signal lines, and EMC is primarily concerned with the lines entering the circuit board.

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What you need to know about PCB design & manufacturing

Category : Uncategorized



Making Your Idea into Reality

Going from prototyping circuits on a breadboard, to designing our own printed circuit board (PCB) is like going off training wheels. There is a lot to know about this process, so let’s dive in.


Buckle your seat belt, Dorothy, cuz Kansas is going Bye Bye. Welcome to the real manufacturing world.

Buckle your seat belt, Dorothy, cuz Kansas is going Bye Bye. Welcome to the real manufacturing world.

PCB design happens during the Electrical engineering (EE) process. EE creates the “brains” of how your device will work. Without electronics, you basically have just a bunch of metal and plastic in your hands.

Things to know before starting the PCB design:

1. PCB size – this depends on your product size (or enclosure size). Product size is defined during electronic engineering design process.

2. PCB layers – the more layers, the more complex the manufacturing of the PCB will be. (Note: even a single layer PCB can be a complex one, but here we are talking about complexity to manufacture the PCBs. The more layers the PCB has, the more costly it will be to manufacture it).

  • 2 layers usually for simple toy products
  • 4 layers usually for IoT related products
  • 6 to 8 layers usually for Smart phone or smart watch.

3. Your PCB manufacturer requirements. Make sure you read the guidelines about pacing, traces size, power isolation, and file naming before you start designing.

Information you will need to provide to the PCB manufacturer:

  • Number of Layers (ex. 2, 4, 6,…etc.)
  • Material (FR-2 (phenolic cotton paper), FR-3 (cotton paper and epoxy), FR-4 (woven glass and epoxy…etc.)
  • Thickness (0.5 mm, 1.0 mm…etc.)
  • Color (Red, Black, Green…etc.)
  • Surface Finish (ENIG (Electroless Nickel/Immersion Gold), DIG (Direct Immersion Gold), OSP (Organic Solderability Preservatives…etc.)
  • Copper Weight (1 oz (35 um), 2 oz (70 um), 0.5 oz (18 um)…etc.)
  • Gerber file


PCB design process:

Circuit Design

For this step you need to create a schematic. It is a document, like a blueprint, that describes how components relate to each other and work together. To create a schematic file, you will need a software tool. We like Quadcept, as it is optimized for designing PCBs for manufacturing (for example, you can export your Bill of Materials (BoM) directly from the tool) and, being cloud-based, it can be conveniently used anywhere. (They also have a free Community Version of the tool for makers and students).

There are also many others you can choose from:

After you have the selected tool installed, you need to get component specifications for each of your selected components. They are usually available on your vendors’ websites. The model files will help you to draw the schematic. When you upload the model to the software tool, the component will be available in the database. Then all you need to do is to follow the data sheet to connect the lines to each pin out of the components. (Note: specifics of the design process will depend on the software tool of choice).

Each schematic symbol needs to have an associated PCB footprint that defines the physical dimensions of the components, and placement of the copper pads or through-holes on the PCB. You should already have your components selected (or select them now), and we covered this procedure in the EE design flow video (See video).

Example schematic

Example schematic


A good schematic is really important, it will serve as a reference file when you do debugging and it is a great communications tool with other engineers. Also, manufacturers can test the device by test points on this document.

PCB Layout + Gerber file

To design PCB layout and create a Gerber file you can use the same software tools that we mentioned for circuit design. Unlike the schematic, PCB layout is allocating the actual components to the exact location on the PCB and show the trace to connect each component together between the PCB layers. As mentioned in the beginning of the article, the higher number of layers you have, the more complex manufacturing it will need and it will be more costly.

Divide the PCB into logical sections according to the functionality (e.g. power supply, audio output, etc.). Then make sure to group the components of each section in the same area. This way you can keep conductive traces short and reduce noise and interference.

User interface (UI) is also something you need to keep in mind when designing your PCB. Locations of the components like audio jacks, connectors, LEDs, etc. need to be adjusted for the best user experience possible.

When you finish the layout design, you produce a Gerber file. This file will be used by your PCBA manufacturer. There are many companies out there that provide these services, and from and from HWTrek’s expert pool we recommend KingbrotherNexPCB and HQPCB.


Example Gerber file

Example Gerber file

Component placement on the PCB is very important. Some components might interfere with each other and cause unexpected behaviors. For example, if you have both, Bluetooth and Wi-Fi modules, they have the same 2.4 Ghz bandwidth and can interfere with each other if not placed correctly.

PCB Fabrication

When you send out your Gerber file to the PCB manufacturer they can print out the circuit board. This will be the basis to build up further, to add the components to the PCB and manufacture PCBA (Printed Circuit Board Assembly).

Unassembled PCB


PCBA (assembled)

PCBA (assembled)

Material preparation

At this point in your EE design, you should already have components selected. You can either ask your PCBA manufacturer to order the required components for you or do it yourself if you have vendors selected. Things to keep in mind:

  • Lead time: as these components come from different vendors, keep in mind the lead time. It can be up to 8-16 weeks for some components.
  • Packaging: order components in reels for SMT machine automatic pick-up, not in separate packages.
  • Minimum Order Quantity: check the MOQ of your component. If you’re buying less than the minimum, make sure the selected components are in-stock. For small quantities (up to 50) you can order online from DigiKey or Mouser. For greater quantities, ask your manufacturer for recommendations.
  • Losses: Order 10% more to account for losses (this does not apply to the expensive components)

Mounting the Components on the PCB

There are two main methods for placing components on the PCB surface:

Through-hole (thru-hole) is manual method of fitting components with wire leads into holes on the PCB surface. It is also often called DIP or Dual In-line Package process. (See the SMT in process in this video.)

SMT (Surface Mount Technology) method is the most widely used in mass manufacturing.  It is done by fast and precise SMT machines that save you time, money, and avoid human error.

Things to remember:

  • Your component type number should not exceed the number of reels the SMT machines of your manufacturer can support.
  • Optimize and consolidate your components, so to have just one SMT run.
  • Check what footprint pad sizes your manufacturer supports. Otherwise the SMT machine will not be able to mount the components correctly.
  • Some bigger components cannot be mounted by the machine and still need manual thru-hole work. Thus, both of these technologies can be used on the same board.
  • Any components that you will need to add manually with thru-hole method, will add to the manufacturing cost.



Reflow soldering is a process that makes the components “stick” to the PCB. The PCBA goes through a reflow oven or an infrared lamp that heats up the board until the solder melts, permanently connecting the components to the board.

The tricky part here is not overheating or damaging the components, as each package has a different thermal profile. A reliable PCBA manufacturer will take care of this process and all you need is to provide the component specifications to them.


Reflow process.

Other soldering methods:

  • Wave soldering is mostly used for the components added manually using the thru-hole method. In these cases, your PCBA will first go through reflow oven and then after adding other components manually, it will go through a wave soldering machine.
  • Iron soldering can be used in specific cases, but not usually in mass manufacturing.

Testing & QA

In this step, a sample of PCBAs will be tested to ensure quality. Common mistakes are: components that are not connected, misaligned components and shorts that connect portions of the circuit that should not be connected. Most common tests:

  • ICT (In-circuit Test). When you design the PCB, you often will reserve some test points for debugging, programming, and other purposes. The ICT machine will use these test points to do the open/short test and will check if the values of the passive components (resistor, inductors, capacitors) are in within specifications.
  • AOI (Automatic Optical Inspection). The manufacturers use “golden sample” – a reference PCBA to compare with others. For this test, the hardware creators will need to provide the specifications and tolerance to the manufacturer to set the parameters.
  • X-ray. The PCBA manufacturers will use X-ray to check the soldering conditions for BGA (Ball Grid Array) components. See X-ray testing in action in this video.

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PCB Design Software – Which One is Best?

Category : Uncategorized

PCB Design Software – Which One is Best?


Article Technical Rating: 7 out of 10

There are numerous software packages available for designing printed circuit boards (PCBs), too many in fact.

That being said, there are three PCB design packages that are the most popular: Altium, Eagle, and OrCAD.

For a struggling entrepreneur or freelance engineer just getting started, all three of these packages are probably prohibitively expensive.

Altium Designer is considered the Ferrari of PCB design packages and starts at over $7,000!  No that is not a typo.  It’s good software, but that’s pretty crazy.

Altium is the most popular PCB design package among those with a company’s budget behind them.  Because of that it’s also the package that many new freelance engineers are most familiar.  A good amount of freelancers splurge on Altium because it’s what they already know.

Most people developing PCBs independently, like entrepreneurs, hackers, and freelance designers, usually can’t afford to shell out that kind of cash on software.

Although significantly cheaper than Altium, neither Eagle or OrCad can really be considered affordable.  OrCad has a price tag of $2,580.  Eagle is a little more affordable at $1,640.

They are all also difficult to use.  Plan on spending at least several days, but more likely weeks, learning how to use any of them (especially Eagle!).

A cheaper, easier to use option is a program called DipTrace, which is what I use for all new designs. One of my favorite things about DipTrace, other than its low price, is that it offers several upgrade levels starting from only $75.  The top package is $895 and allows designs of unlimited size.

Each level increases the maximum number of pins and signal layers allowed.  You can start with the $75 Starter version and work your way up as needed.  You only pay the difference between each level.

PCB Design Software Pricing Comparison

So Who Exactly Needs PCB Design Software?

Let’s look at the types of people most likely to need a PCB design tool.  I’ll discuss four groups of people likely to use circuit design software, although I’m sure there are several more:

GROUP #1 – Corporate engineers – Most established companies can easily afford to spend thousands of dollars on software.  Altium is probably the right choice for you.

GROUP #2 – Independent freelance engineers – If you already know how to use Altium from a previous corporate job, and you can afford it, then Altium may be your best choice.  If not, then then DipTrace is probably your best choice, unless you need to collaborate with other engineers.  If you collaborating with other engineers is critical then you’ll probably be better off with one of the more popular packages.

GROUP #3 – Engineer entrepreneurs – If you have prior experience designing electronics (or wish to learn how) then you may be better off designing your product yourself.  Or at least as much as possible.  DipTrace is definitely the way to go for you!

GROUP #4 – Electronic hobbyists and hackers – Whether you’re developing a circuit for fun or for profit, DipTrace is easily the best design package for you.

The Most Important Criteria for PCB Design Software

For me, as well as most entrepreneurs and a majority of freelance engineers, there are five primary criteria that matter most when selecting a circuit design software package:

CRITERIA #1 – Must be intuitive to use – DipTrace is the clear winner when it comes to being intuitive to use.  Using DipTrace you’ll be able to begin designing your circuit almost immediately with a very minimal learning curve.  No need to waste hours reading a boring manual with DipTrace,

Eagle is the clear loser in regards to being intuitive to use.  It has the worst user interface of just about any design package I’ve ever used.  Eagle is utterly frustrating to learn and you’ll waste days or weeks trying to learn it.  In fact, it will probably be many weeks before you are actually comfortable with it, if ever.

CRITERIA #2 Must be reasonably priced – DipTrace is easily the most affordable PCB design package.  It is only half the price of Eagle, or only an eighth the price of Altium.  DipTrace also has a low barrier to entry because you can begin with their low-cost Starter version and upgrade your way up as needed.

CRITERIA #3 Needs to have all of the features you’ll ever need, but not every feature you could ever imagine – There is no clear winner here, and it really depends on your needs.  That being said, DipTrace has had every feature I’ve ever needed.

CRITERIA #4 Ideally it should be a “standard” and in widespread use.  Altium is the clear winner for this criteria, with Eagle in second, OrCad in third place, and DipTrace coming in last.

CRITERIA #5 Large libraries of components available.  All four packages come with huge libraries of components.  Large libraries are critical because creating new components can introduce errors that won’t be captured by any of the verification tools.  That being said, regardless of the package, you’ll eventually need to create some custom components yourself.

Because they are so popular, Altium and Eagle are probably the winners for this criteria because component manufacturers are more likely to provide a component library for one of these two packages.  This has never really been an issue for me and I’ve found DipTrace’s libraries to be quite extensive.

The Ultimate Cost of Complicated Software

While designing microchips for Texas Instruments (TI) we used a package from Cadence (makers of OrCad) which cost TI probably millions in licensing fees.

Honestly, it was horrible software that was very confusing and difficult to use.  So it also cost an incredible amount in lost design time from engineers.  In general, it took new designers several months to get really efficient in its use.

Not so with DipTrace.  If you’ve ever done any circuit design or PCB layout you can sit down with DipTrace and be producing quality designs within a few hours.  At the other extreme is Eagle which will cost you weeks of lost design time.  Can you tell I really don’t like Eagle?

Some Details About DipTrace

DipTrace consists of four separate modules.  One for schematic entry, one for PCB layout, one for creating new components, and one for creating new PCB landing patterns.

DiptraceMainMenuDipTrace Opening Menu

The DipTrace schematic capture module is an advanced circuit design tool that supports multi-sheet and multi-level hierarchical schematics.  Circuits can be easily converted to PCB and back annotated. Verification and Spice export for simulation allow for full project analysis.

ScreenHunter_310 Jul. 13 12.37DipTrace’s Schematic capture module

The DipTrace PCB layout module offers smart manual routing, shape-based autorouting, advanced verification, and 3D previewing.

Design rules can be defined by net classes, class-to-class rules, and detailed settings by object types for each class or layer. DipTrace features a design process with real-time DRC, which reports errors on the fly before actually making them.

The board can be previewed in 3D and exported  for mechanical CAD modeling. Design Rule Check (DRC) with in-depth detailing, net connectivity verification, and comparing to source schematic ensure maximum quality of the final design.

ScreenHunter_311 Jul. 13 12.41DipTrace’s PCB layout module

The DipTrace component editor is for creating schematic symbols for any components not included in DipTrace’s library of components.

The DipTrace pattern editor is for the creating PCB landing patterns for these new components.

The main negative I’ve found with Diptrace is that’s not as standard as Altium, Eagle, or OrCAD which can be an issue if you ever want to work with other engineers on a project.

For example, you may want to design the schematic circuit, but have someone else do the PCB layout for you.  This becomes challenging with DipTrace.  Most PCB layout engineers use Altium, Eagle, or OrCad and it’s very problematic to switch between software packages on a project.

You can design the schematic in DipTrace, but if you wish to outsource the PCB layout the schematic will probably need to be exported to a PDF file, then manually redrawn in the new software package by the PCB layout engineer.  Of course, there are plenty of engineers that do use DipTrace (like myself), so this isn’t always necessary.

DipTrace can import schematics and PCB layouts from Eagle and OrCad (but not Altium); however, it can’t export to these formats.  Each PCB software package tries to make it difficult for you to export to another package because they don’t want to lose you as a customer.

What About Free PCB Design Software?

Free PCB design packages do exist but I don’t generally recommend them. Some PCB suppliers offer their own proprietary PCB design tools. These tools are free but they usually only work with that specific PCB supplier.

So if you start a design using one of these free supplier-specific tools then you are usually “stuck” using that supplier.  Limiting your supplier options to a single company is not generally a good idea. By using these free tools you are boxing yourself in a corner that may be hard to break from later.

That being said, DipTrace, Eagle, and OrCad all offer free versions of their software. The free versions are severely limited in how complex of a design you can create, but they allow you to test them out before forking over the cash for their paid versions. Altium offers a limited-time free trial of its software.

So if you have any doubts which package is right for you, then I highly recommend that you download and test their free versions first. Most likely you won’t be able to create your entire design, unless it is unusually simple, but it will let you decide which package is best for you.


If you test out the free versions, I think you will find that DipTrace is the only one intuitive enough to allow you to create your design immediately without spending hours reading the manual. Most likely, unless you read the manuals, you will get very frustrated trying to use Eagle, OrCad, or Altium.  Although I’ve found Eagle to be the most frustrating to use.

So to summarize, if you’re looking for something easy to use and affordable then go with DipTrace.  If you need to work with other engineers on the same project then Altium (or Eagle) is probably the best choice.



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PCB Designers Need to Know These Panelization Guidelines

Category : Uncategorized


Unplanned delays and redesigns can be avoided by following common-sense PCB processing edge and array guidelines, as well as understanding the basics of the assembly methods.

Senior Manufacturing Engineer, PC Board Assembly Department, AMETEK

This article provides common-sense printed-circuit-board (PCB) processing edge and array guidelines that should give most assemblers a good chance at efficiently populating the PCB assemblies (PCBAs) as designed. These guidelines are intended for PCB designers, who must understand the basics of assembly methods (including panelization concepts) applicable to their designs if there’s any hope they will consistently turn out manufacturable board designs. These are also targeted at the PCBA process technician trainee, so he or she will know what to ask for in a PCB array design.Guidelines spell out when to create arrays or add processing edges; the proper sizes for arrays and processing edges; the type of breakout design that should be used under given circumstances; and how to arrange breakouts to prevent damage to individual PCBs when breaking them out of the array or while removing processing edges.

This article uses the terms array and panelization interchangeably, whichever seems to fit best at that time. It’s also common to use the term “matrix” for an array of PCBs. It can get confusing, because the word “panel” is reserved for the standard-size laminate piece used by the PCB fabricator, whereas the word “panelization” indicates a method of designing an array of PCBs into a single processing piece for the PCB assembler.

It’s impossible to come up with a set of hard rules for all due to the differences in machine technologies from one assembly shop to another. In addition, the PCB construction and thickness can play a major role in what rules to use. To satisfy a variety of assembly shops and PCB construction technologies, the PCB design has to be more robust—stronger panels, more clearance of all types, more robust board finishes, etc. If you have a captive assembly shop, you will have the flexibility to adjust some of the guidelines, according to the assembler’s unique capabilities, when product design density dictates the need.

PCB Processing Edge or PCB Array

Small boards

Most production machinery, paste printers, pick-and-place machines, AOI equipment, selective soldering machines, wave-solder machines, transfer conveyors, etc., cannot process boards with less than a 2.0-in. (50.8mm) conveyor width. So when the longest side of a rectangular PCB is less than 2.0 in., you must either add processing edges to make it bigger or create an array of boards, or a combination of the two.

Odd-form boards

When a PCB needs to fit into an odd-form space and doesn’t have two parallel edges for processing on conveyors, one must somehow add the necessary processing edges. These make for some pretty interesting and complex array designs, keeping in mind how the boards will be depanelized and how board cost is minimized by making them fit well on the fabricator’s standard processing panel. These considerations are covered below.

Note: You do have the option of using an adjustable or custom-made board carrier, but these options are pretty expensive and cumbersome. They can also be maintenance-intensive and use up significant floor space.

Board-Array Dimensions

You should design your PCB array to secure the benefits of running multiple boards through your processes, while yielding the maximum number of boards from the PCB fabricator’s standard processing panel. Every cut in the array that’s made to facilitate future PCB breakout will weaken the panel somewhat. Therefore, you must also limit the size of the array to prevent PCB-array weakness, which can cause vibration in the pick-and-place machine and sagging in the wave-solder machine.

The typical PCB manufacturer runs a standard panel size of his choice, very commonly 18 × 24 in. They will want a 1/2-in. perimeter clearance for handling the panels when processing double-sided boards and a 1-in. clearance when processing multilayer PCBs. On an 18- × 24-in. panel, this translates to 17 × 23 in. of usable panel space for double-sided and 16- × 22-in. inch panel space for multilayer boards. They will need about 0.1 in. of routing space between board arrays, so this is also unusable panel space. A number of “panel calculators” are available for use to help maximize the board count you get from the fabricator’s standard panel; however, if you don’t get 70% usage, you should try harder (Fig. 1).

1. When designing the panel size, consider these array-width dimensions as a template to keep the conveyor-width changes to a minimum. This is especially important in low-quantity, high-mix environments.

The other item to consider when designing the panel size is to keep the conveyor width changes to a minimum. This is especially important in the low-quantity, high-mix world in which I live. If you’re running millions of identical boards down a line, then this isn’t a big concern.

In one example of limiting the conveyor width changes, the following array widths were developed to use the 24-in. dimension of the fabricator’s panel efficiently with a 1-in. perimeter handling clearance:

W = 3.75 in., L ≥ W

W = 7.25 in., L ≥ W

W = 10.75 in., L ≥ W

The length of the array is then subject to the 16-in. limitation of the 18-in. panel edge.

Panelization Methods

The design of the board—namely how much component clearance is provided on the edges, whether sensitive SMT components are close to an edge, and whether or not connectors or other components hang over an edge—will limit the choices of panelization breakout methods from which to choose. Sometimes a combination of methods is appropriate to secure the PCB-array strength, while providing a viable breakout method.

To improve strength, increase the board count on the fabricator’s panel, and facilitate automated depaneling, arrays can be designed with solid tabs between boards in just about any orientation. The depaneling method for this kind of panel is either a depaneling router or a laser-cutting machine. The former creates vast amounts of dust, noise, and vibration, and requires firm holding fixtures. The latter is capital-intensive and limited to board thicknesses of about 1 mm. Still, these methods have their place in the high-volume market and aren’t subject to many of the restrictive guidelines to be outlined later.

The solid tabs between boards can be removed with a hook-shaped blade tool, but this process can be troublesome. Even with very little clearance of the blade in the slot between boards, it can rotate and take a bite out of the good part of the board. If the blade-cutting edge is tapered to prevent board damage, it leaves a little of the tab protruding from the good board. It’s also a very inefficient process.

The two preferred depanelization methods for the low-volume/high-mix arena are V-grooves and perforated tabs. Tabs and V-grooves are pretty well covered in the IPC standards.

V-Groove Panelization Method

Generally speaking, this calls for cutting 1/3 the thickness of the board from the top and 1/3 the thickness from the bottom, collinear with the top cut, with a 30- to 45-degree circular cutting blade. A machine is needed to depanel it, as the remaining 1/3 of the board thickness left intact is surprisingly strong, and breaking it off by hand would put severe stress on the PCB.

2. V-grooves tend to cause a wide variety of problems in board design and PCB manufacturability.

Many prefer the V-groove method (Fig. 2) where possible (in which no components hang over the edge), because it’s more efficient and produces less surface stress when using a properly designed machine known as a “pizza cutter.” Also, the pizza-cutter-type depaneling machines for V-grooves are inexpensive, last forever, and require very little adjustment and maintenance. Furthermore, they’re portable—you can mount the depaneling machines on a small cart and easily move them around the shop wherever they’re needed.

However, this is the most restrictive method of panelization. For example, you can’t use a V-groove breakout method where components are hanging over the edge. Even if they’re too close to the edge of the board, you can’t use this method unless you’re cutting a straight line all the way through the PCB array.

To clear the circular cutting blade, you must maintain 0.05-in. clearance from components to the center of the V-groove score, taking into consideration component size and mounting variations. Tall components, such as radial capacitors, radial inductors, and power-dissipating radial ceramic resistors, would have to be spaced greater than 0.05 in. (nominal) because of position variation, whereas connectors and other low-profile parts may be placed at 0.05-in. clearance.

Surface-mount multilayer ceramic chip capacitors (MLCCs) must be oriented with the long side parallel to the V-groove cut if less than 0.25 in. (6.35 mm) away from the score line and kept 0.119 in. (3 mm) away regardless. This becomes more important with the larger-size caps and with certain cap dielectrics. The surface stress, caused by forcing the depaneling blade into the V-groove, transfers through the board surface to the rigid solder joints, and then to the component bodies. This can fracture them if they’re too close to the V-groove. Orienting the long edge of the capacitor body parallel to the edge minimizes the risk of body fracture (Fig. 2, again).

V-grooves can also weaken a PCB array, which is very undesirable when the array must go through a wave-solder machine. The surface tension of the solder wave, pulling down on the preheated PCB material, is exacerbated by V-grooves in the array. When the board is pulled down, the protruding leads tend to run into, and sometimes get hung up, on the wave-solder baffle.

3. In the case of a rectangular PCB, strengthen the array by “jump scoring” on the shorter, or leading and trailing, edges.

In the case of a rectangular PCB, you would strengthen the array by “jump scoring” on the shorter, or leading and trailing, edges (Fig. 3). Since the V-groove blade is circular, you must cut beyond the edge of the board to achieve a full-depth V-groove at the edge of the board. Running the cut 1/4 in. past the edge of the PCB, halfway through a 1/2-in. breakaway edge, will leave enough of the leading and trailing edges to strengthen the array and minimize the pulling down effect of the wave, while achieving the desired full depth V-groove cut on the board.

When jump scoring is used, the depaneling operators must be instructed to remove the leading and trailing edges before trying to separate the boards. You may get some push back from the PCB fabricator, but it gives you a stronger array. Give the fabricator a break by not dimensioning the end of the jump score. It’s hard to control, and you don’t know the V-groove cutting-blade diameter. So you don’t know exactly where the cut will end.

Note: The V-groove method is undesirable if a “clean,” smooth board edge is required, but this is rarely the case.

Breakaway-Tab Panelization Method

When V-grooves can’t be used, design PCB arrays, leaving perforated tabs routing space between PCBs. Keep traces and surface-mounted parts 1/8 in. or about 3 mm away from the perforation holes in the tabs to avoid damage from splintering and surface stress during board separation. Keep the SMT MLCCs 1/4 in. (6.35 mm) away from the perforated-tab holes. Standard router size is 3/32 in. or 2.5 mm in most fabrication houses, and you want to design a spacing that requires a single pass of the router bit. Where array weakness was a consideration for V-groove designs, it’s doubly so for perforated-tab arrays.

A five-hole perforation pattern is standard for breakaway tabs. Three-hole patterns, which are for knockouts, may be used where trace or component edge clearance is limited and where tabs must be placed under overhanging parts. The three-hole breakouts, being much weaker, must be spaced closer together than the five-hole breakouts.

Removable knock-outs are required to fill holes with area greater than or equal to 0.6 in.2, to prevent the solder wave from running onto the top of the board. In the case of a relatively small, rectangular knockout, a single five-hole breakout tab may be placed on any one side. Since PC boards will sag in the middle over the wave, knockouts are more important toward the middle of the board and less important toward the edges. If the wave-solder process isn’t necessary, the knockouts aren’t required.

4. The breakout tab specifications, adapted from IPC-7351, are designed to prevent the leftover material from the tab perforations from protruding past the PCB edge after breakout.

The breakout-tab specifications, adapted from IPC-7351 (Fig. 4), are designed to prevent the leftover material from the tab perforations from protruding past the PCB edge after breakout. This may cause some headaches for the PCB designer when running traces near the board edge, but it can usually be accomplished if kept in mind from the beginning of the board design.

Perforated holes, centered in the routed cutout, will cause unwanted side board protrusions (Fig. 5).

5. Perforated holes, centered in the routed cutout, will cause unwanted side board protrusions.

Three-hole perforated tabs are used for knockouts and for board edges when there’s not enough room for five-hole perforated tabs. A rectangular knockout can be designed with a five-hole perforated tab on any single edge (Fig. 6).

6. Three-hole perforated tabs are used for knockouts and for board edges that don’t have enough room for five-hole perforated tabs. A rectangular knockout can be designed with a five-hole perforated tab on any single edge.

Do not place breakaway tabs under overhanging components (Fig. 7).

7. Don’t place breakaway tabs under overhanging components.

Tabs must be placed as close to the ends of the panel as possible to prevent “whale finning” (Fig. 8) and thereafter, every 2 to 3 in. for five-hole pattern or 1.5 in. for three-hole perforated tabs. Three-hole pattern breakouts are used on board edges where space and clearance prevents use of five-hole breakouts.

8. The surface tension of the solder on the wave will pull down unsupported parts of the PCB and cause topside solder flooding. Place breakout tabs near the ends of the processing edges to prevent “whale finning.”

Three-hole pattern breakouts are used on board edges where space and clearance prevents use of five-hole breakouts.

The breakaway panels must be designed so that all tabs broken at one time are collinear. Another way to state it is that the break axis must be collinear with the tab hole perforations involved in any one break. If the tab perforations aren’t collinear during the breaking operation, some tabs will experience a force perpendicular to the board surface, causing a tearing action on the surface lamination (Fig. 9).

9. If the tab perforations aren’t collinear during the breaking operation, some tabs will experience a force perpendicular to the board surface, causing a tearing action on the surface lamination.

It could be just the solder-mask layer that delaminates and gets separated from the traces, or it could actually be the surface layer of the board that tears and pulls up any traces with it. This is a main complaint against the perforated-tab method of panelization. At AMETEK, we have found a breaking method that will never damage a board, which is described below. In practice, though, this method IS NOT foolproof.

Combining Panelization Methods

Putting the guidelines together for the V-groove and perforated-tab panelization methods, let’s look at two array designs for the same board (Fig. 10).

10. While combining panelization methods reduced the board count in this example, it was worth the slight addition in cost for more PCBs to prevent board damage that kept occurring during breakout, as well as recurring problems with wave-solder overflow.

The good design reduced the board count on the fabricator’s panel. However, it was well worth paying slightly more for the PCBs in order to prevent the board damage that kept occurring during breakout and the problems with the wave-solder overflow.

Critical Instructions for Breaking Out Boards with Perforated Tabs

No matter how well you design a perforated-tab PCB array, the possibility exists for tearing or splintering the solder-mask layer, or the active surface layer, of the PCB if a poor method of break out is used. The following is a safe method of breaking out perforated-tab arrays, to both minimize PCB damage and the stresses transferred across the PCB’s surface to the components during breakout (Figs. 11 and 12).

11. Bend each tab on the edge until you hear it crack, but no further. We don’t want the edge to break all the way off at this point

12. Bend the processing edge in the opposite direction to completely remove it from the board.

Panel-Strength Considerations for Multiple Board Arrays

The main reasons for maintaining overall panel strength is to avoid vibration in the pick-and-place machine and droop during wave soldering and selective soldering. The rules outlined below may be relaxed by 50% if the panel will not be subjected to any form of through-hole machine soldering. They also may be relaxed if the panel will be soldered on a supporting pallet. Following are some guidelines to assure sufficient panel strength to withstand processing stresses.

V-groove scoring or breakout tabs with routing between boards cause significant reduction in panel strength. The number of V-grooves or routings between boards on a multiple image pallet must be limited, depending on:

• Board material and thickness

• Weight of parts to be installed on the board

• Whether or not the boards will be processed through soldering machines, using a rigid soldering pallet

Multiple board panels must be designed in a way to provide leading and trailing unscored stiffener edges. Use jump scoring, as described earlier in the article, as necessary. If heavy parts must be hand-soldered because they can’t withstand automated soldering processes or because they’re on the bottom side of the board, they’re not a factor in panel design decisions.

For FR4 or HTFR4 PCBs greater than or equal to 0.06 in. (1.5 mm) thick, allow no more than five boards, side by side, up to 1.5-in. board width, four boards up to 2.5-in. board width, three boards up to 4-in. board width, and two for boards up to 7.5-in. board width.  Boards up to 6.65 in. long may be turned 90° on the panel and placed side by side along the long axis of the array to fit within the standard 7.25-in. width. This only makes sense if the resulting panel is longer than it is wide, so you can add boards to the array to utilize the fabricator’s panel efficiently (Fig. 13).

13. Long boards may be placed side by side along the long axis of the overall panel.

You may also attempt to rotate longer boards, up to 10 in. long, 90° to fully utilize the fabricator’s panel. However, that usually results in excessive array droop during through-hole machine soldering. Rotating the longer boards is more practical on thicker, more robust PCBs. When designing the standard, 0.09-in.-thick PCBs, the board count can increase in the arrays above these guidelines.

For FR4 or HTFR4 PCBs less than 0.06 in. (1.5 mm) thick, allow no more than three boards side by side, up to 1.5-in. board width, and two boards, up to 3-in. board width. Note that these panels will be extremely fragile and still not be wave-solderable without being supported by a wave pallet.

Another consideration during PCB-array design, to avoid drooping in processing machines, is the weight of the parts on the board. If the boards will have heavy magnetics (greater than a half a pound or 1.1 kg) or other massive parts on them, it’s best not to put multiple boards on a panel. Two boards with heavy parts may be placed side by side if the resulting panel width is no more than 7.25 in. In this case, it’s best to specify a thicker PCB, say 0.09 in.

Miscellaneous Considerations

Odd-shaped PCBs: Odd-shaped boards may be rotated with respect to each other to reduce PCB raw material waste, thus reducing board cost. It’s acceptable to alternate the images, 90° to 180° from each other, to realize the savings in PCB material, as long as you don’t violate the rule about breakout tab perforations being collinear with each breakout axis.

Tooling holes: To facilitate bed-of-nails testing, provide tooling holes near any three corners of the board arrays on the breakaway processing edges. Tooling holes are typically 0.125 in., +0.004/-0.00, and are unplated. Also, tooling holes are usually placed about 5 mm from the edge of the board-array edges.

Fiducial marks: Arrays that contain PCBs with surface-mounted parts must have fiducial marks, typically one near each tooling hole. There are many choices for fiducial-mark formats, so you should consult your assembler for their preference. The edges of the fiducial marks must be at least 0.157 in. (4 mm) from the board edges so that they don’t get obscured by conveyor top clamps in the processing machines with fiducial-alignment camera systems. The array processing-edge fiducial marks don’t preclude the necessity of providing fiducial marks on the individual boards within the array.


No designer can afford to ignore such PCB panelization considerations. PCB-array designs may dramatically impact, either positively or negatively, the PCB assembly process. The various considerations are complex and will be affected by PCB geometry, as well as the myriad of machine capabilities of countless PCB assembly service suppliers. PCB cost can also be significantly affected by the array design.

The above guidelines aren’t set in cement, but they work for us as good practice in AMETEK production applications. You should always try to connect with your PCB assembly service to become familiar with its capabilities and machine process requirements. But since this is often impossible during the design phase of PCBs, try to design on the robust side to improve your chances of achieving an efficient assembly process.

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The Engineer’s Guide To High-Quality PCB Design

Category : Uncategorized

Eventually, almost every EE must design a PCB, which isn’t something that’s taught in school. Yet engineers, technicians, and even novice PCB designers can create high-quality PCBs for any and every purpose with confidence that the outcome will meet or exceed the objective.

Virtually every electronic product is constructed with one or more printed-circuit boards (PCBs). The PCBs hold the ICs and other components and implement the interconnections between them. PCBs are created in abundance for portable electronics, computers, and entertainment equipment. They are also made for test equipment, manufacturing, and spacecraft.
Fly-Buck Converter PCB Layout Tips Fly-Buck Converter PCB Layout Tips
High-Density PCB Layout of DC/DC Converters High-Density PCB Layout of DC/DC Converters

Eventually, almost every EE must design a PCB, which isn’t something that’s taught in school. Yet engineers, technicians, and even novice PCB designers can create high-quality PCBs for any and every purpose with confidence that the outcome will meet or exceed the objective. Also, these designs can be completed on schedule and within budget while meeting the design requirements. Designers just need to mind the essential documentation, design steps and strategies, and final checks.

The Basic Design Process

The ideal PCB design starts with the discovery that a PCB is needed and continues through the final production boards (Fig. 1). After determining why the PCB is needed, the product’s final concept should be decided. The concept includes the design’s features, the functions the PCB must have and perform, interconnection with other circuits, placement, and the approximate final dimensions.


1. The ideal PCB design flow begins when designers recognize a need that must be fulfilled, and it doesn’t end until testing verifies that the design can meet those needs.

Ambient temperature range and concerns regarding the operating environment should be addressed and used to specify the materials selected for the PCB. Components and PCB materials must be selected to guarantee operation under all expected and potential forms of duress the board may be exposed to during its lifetime.

The circuit schematic is drawn based on the concept. This detailed diagram shows the electrical implementation of each function of the PCB. With the schematic drawn, a realistic drawing of the final PCB dimensions should be completed with areas designated for each of the circuit’s schematic blocks (groups of components closely connected for electrical reasons or constraints).

Bill Of Materials

Simultaneously with the schematic’s creation, the bill of materials (BOM) should be generated. The components in the circuit should be selected by analyzing the maximum operating voltages and current levels of each node of the circuit while considering tolerance criteria. With electrically satisfactory components chosen, each component should be reconsidered based on availability, budget, and size.

The BOM must be kept up-to-date with the schematic at all times. The BOM requires the quantity, reference designators, value (numeric value of ohms, farads, etc.), manufacturer part number, and PCB footprint for each component.

These five requirements are critical because they define how many of each part are needed, explain identification and circuit locations while exactly describing each circuit element used for purchasing and substitution, and explain the size of each part for area estimations. Additional descriptions may be added, but it should be a condensed list describing each circuit element, and too much information can over-complicate library development and management.

PCB Documentation

The PCB’s documents should include the hardware dimensional drawings, schematic, BOM, layout file, component placement file, assembly drawings and instructions, and Gerber file set. User guides also are useful but aren’t required. The Gerber file set is PCB jargon for the output files of the layout that are used by PCB manufacturers to create the PCB. A complete set of Gerber files includes output files generated from the board layout file:

Silkscreen top and bottom
Solder mask top and bottom
All metal layers
Paste mask top and bottom
Component map (X-Y coordinates)
Assembly drawing top and bottom
Drill file
Drill legend
FAB outline (dimensions, special features)
Netlist file

The special features included in the FAB outline include but are not limited to notches, cutouts, bevels, back-filled vias-in-pad (used for BGA-type IC packages that have an array of pins under the device), blind/buried vias, surface finish and leveling, hole tolerances, layer count, and more.1

Schematic Details

Schematics control the project, so accuracy and completeness are critical for success. They include information that is necessary for the proper operation of the circuit. A schematic should include adequate design details, such as pin numbers, names, component values, and ratings (Fig. 2).


2. Proper schematics, such as this one for the IDTP9021R wireless power receiver’s buck regulator block, include pin numbers, names, component values, ratings, and other vital details.

Embedded within each schematic symbol is the manufacturer part number used to determine price and specifications. The package specification determines the size of the footprint for each component. The first step should be to make sure the exposed copper for each pin is in the proper location and is slightly larger than the component pins (3 to 20 mils) depending on available area and soldering method.

Consider assembly when designing footprints, and follow the manufacturer’s recommended PCB footprint. Some components come in microscopic packages and do not allow room for extra copper. Even in these cases, a stripe of 2.5 to 3 mils of solder mask should be applied between every pin on the board.

Follow the rule of 10. Small vias have a finished hole size of 10 mils with 10 additional mils of pad ring. Traces should be 10 mils or further from the edge of the board. Trace-to-trace pitch is 10 mils (5-mil air-gap, 5-mil trace width, 1-oz copper). Vias with 40-mil diameter holes or larger should have a pad ring added for reliability. An additional 15 to 25 mils of clearance beyond the design rule should be instated for copper planes on outer layers from plane to pins. This reduces the risk of solder bridging at all solder points.

Component Placement

Component placement is next in the process and determined based on thermal management, function, and electrical noise considerations. A first-pass component placement step commences after the outline of component and interconnect position has been assigned. Immediately after the individual components are placed, a placement review should be held and adjustments made to facilitate routing and optimize performance.

Placement and package sizes are often reconsidered and changes are made at this point based on size and cost. Components absorbing greater than 10 mW or conducting more than 10 mA should be considered powerful enough for additional thermal and electrical considerations. Sensitive signals should be shielded from noise sources with planes and be kept impedance-controlled.

Power management components should utilize ground planes or power planes for heat flow. Make high-current connections according to the acceptable voltage drop for the connection. Layer transitions for high current paths should be made with two to four vias at each layer transition.Place multiple vias at layer transitions to increase reliability, reduce resistive and inductive losses, and improve thermal conductivity.

Thermal Issues

The heat generated by the IC is transferred from the device to the copper layers of the PCB (Fig. 3). The ideal thermal design will result in the entire board being the same temperature. The copper thickness, number of layers, continuity of thermal paths, and board area will have a direct impact on the operating temperature of components.


3. IC thermal conduction can be achieved through the use of thermal vias and copper planes.

To reduce operating temperatures easily, use more layers of solid ground or power planes connected directly to heat sources with multiple vias. Establishing effective heat and high-current routes will optimize heat transfer by means of convection. The use of thermally conductive planes to spread the heat evenly dramatically lowers the temperature by maximizing the area used for heat transfer to the atmosphere (Fig. 4).2


4. Effective heat spreading can distribute the heat uniformly from a heat source to all of the PCB’s exposed surfaces.

With even heat distribution, the following formula can be used to estimate surface temperatures:

P = (heatConvection) x area x (ΔT)


P = power dissipated on the board

Area = board (X axis x Y axis)

ΔT = surface temperature – ambient temperature

HeatConvection = convection constant based on ambient conditions

Fine-Tuning The Component Placement

Components should be placed in the following order: connectors, power circuits, sensitive and precision circuits, critical circuit components, and then the rest. The schematic is built around each part on the PCB and completely interconnected. Routing priority for the circuit is chosen based on power levels, noise susceptibility, or generation and routing capability.

In general, trace widths of 10 to 20 mils are used for traces carrying 10 to 20 mA and 5 to 8 mils for traces carrying less current than 10 mA. High-frequency (greater than 3 MHz) and rapidly changing signals should be carefully considered when routed along with high-impedance nodes.

The lead engineer/designer should review the layout, and physical locations and routing paths should be adjusted iteratively until the circuit is optimized for all design constraints. The number of layers depends on power levels and complexity. Add layers in pairs since the copper cladding is produced that way. The routing of power signals and planes, the grounding scheme, and the board’s ability to be used as intended all influence operation.

Final inspections should involve verification that sensitive nodes and circuits are properly shielded from noise sources, solder mask exists between pins and vias, and the silkscreen is clear and concise. When determining layer stack-up, use the first inner layer below the component sides as ground and assign power planes to other layers. Stack-ups are created in a manner that balances the board relative to the midpoint of the Z axis.

Consider any concerns the PCB designer has during the reviews, and correct the PCB based on feedback generated by the reviews. Create and verify lists of changes during each review iteration until the board is finalized. During all stages of the layout, keep the design error free by using the design rule checker (DRC).

The DRC can only catch errors that it has been programmed to monitor, and DRC rule sets often change based on individual designs. At the minimum, the design rule checking should cover package-to-package spacing, unconnected nets (a unique name identifying each node of the circuit), shorted nets, air-gap violations, if vias are too close to solder pads, if vias are too close to each other, and vertical clearance violations.

Many other important DRC rules can be set to ensure a robust design, and they should be researched and understood. For example, keep clearances at or above 5 mils. Vias should not be located within surface-mount pads (unless back-filled). And, solder mask should be between all solder points.

Cost is often a driving influence behind PCB design, so it is good to understand the cost adders in PCB manufacturing. A typical board is two to four layers, with no drill holes less than 10 mils in diameter and 5-mil minimum air gaps and trace widths. It also should be 0.062 in. thick with standard FR-4 and a copper foil weight of 1 oz. Additional layers, extra thick or thin boards, vias-in-pad, back-filled vias (non-conductive preferred due to conductivity limitations and thermal expansion differences), blind/buried vias, and lead time all substantially add to the overall cost.

Manufacturer capabilities should be understood when the PCB design commences. PCB fabs are routinely contacted about capabilities and cost reduction techniques when designing PCBs for manufacturability.


PCB design may be complex, but it is quite possible to design good boards with a little technique and practice. Using these guidelines and adding research when needed, seasoned veterans may continue honing their skills and novice designers may learn to create high-quality PCBs that exceed expectations.