EMI and Signal Integrity: How to Address Both in PCB Design

  • 0

EMI and Signal Integrity: How to Address Both in PCB Design

Category : Uncategorized


toc_F1_shutterstock_170100419Let’s do a comparison of EMI (electromagnetic interference) design and signal integrity. EMI focuses on the associated specifications and testing requirements and interference between neighboring equipment. Signal integrity addresses the degradation of signal quality to the point where erroneous results occur. But the overlap in design techniques at the board level is considerable. Note that the IEEE EMC Society has a subcommittee devoted to signal and power integrity.

We consider signal integrity to be EMI at the circuit board level. Our experience is that a circuit board that is well designed for signal integrity is generally pretty good for EMC as well. Let’s take a closer look at these issues, and see where they differ and where they overlap.

Different Focus, Similar Techniques

With signal integrity, the focus is on printed circuit board and associated interconnections between circuit boards. The objective is clean signals along with adequate operating margins (timing, supply voltage, and environmental variations). This has become a major factor with the increasing serial I/O speeds, headed to 100 GHz. The key concerns are signal reflections, crosstalk, ground bounce and power decoupling. The solutions are careful circuit layout and attention to timing. The interference levels of interest are millivolts and milliamps.

EMC focuses on the entire system, including printed circuit boards, enclosures and cables and power supply. The objective is to pass relevant EMC test requirements and to make sure it works in its intended application. The key concerns are emissions, immunity, and mutual compatibility of equipment, including digital and analog circuits, motor controls, relays, etc. The remedial solutions are careful circuit layout, grounding and shielding, filters and transient protection. The relevant signal levels are microvolts and microamps for emissions, and kilovolts and amps for immunity.

The common area is at the circuit board and local interconnect area. Even here, there are some clearly different aspects of interest. First, note that the key signal levels of concern are very different. For signal integrity, the key factor is to keep noise levels substantially below the signal levels, so our noise margins are in the millivolt range for digital circuits. But, for EMI, emission levels must be kept in the microvolt and microamp range, typically three orders of magnitude lower than acceptable internal noise levels. For immunity, external levels may well be in the kilovolt and amp range, again, orders of magnitude higher than logic levels and analog circuit levels.

This means that parameters entirely acceptable with signal integrity can be grossly higher than that needed for emissions and grossly lower than needed for immunity.

Parasitic coupling paths are more critical for EMI, but signal losses are more critical for signal integrity.

Let’s see how these factors affect board design.

Ground Impedance

Ground impedance is at the root of virtually all signal integrity and EMI problems; low ground impedance is mandatory for both. This is readily achieved with a continuous ground plane, and exceedingly difficult with traces, as would be used in a two layer board. We’ll deal with multilayer boards, where it is feasible to implement a ground plane.

Ground impedance is an important issue for both signal integrity and especially for high frequency emissions in EMI. A ground plane serves well as a signal return, provided the ground is continuous under the signal path. But, even with a continuous return path, there will be enough voltage drop across ground to generate a common mode voltage. This is not significant for signal integrity, but is the primary cause of common mode voltages which, left unchecked, will escape as an EMI emitter via the signal or power ground conductor.

Here, we note that common mode currents are purely parasitic. They contribute nothing to the desired signal but can be difficult to block as EMI emitters. Differential mode currents are the normal signal path, and are more of an issue with signal integrity than with EMI. These considerations are driven by the loop area; inductive impedance of the signal/return loop is proportional to the loop area, as is the antenna efficiency (a consideration for radiated emissions and immunity). But signal/ground loop areas on a multilayer circuit board are small, providing the return path in ground is continuous, and is usually not a problem with EMI.

Copper thickness is not an important factor. At high frequencies, skin effect dominates, so currents are squeezed to the surface, rendering extra thickness irrelevant.

In fact, the principal problem with ground impedance is the discontinuities that occur in the signal return path, and that has major impact on characteristic impedance control.

Impedance Control

At higher frequencies, characteristic impedance control becomes necessary for signal integrity and, to a lesser extent, for EMI control. Now we are operating well into the GHz range, and impedance control requires meticulous care just to maintain signal integrity. For EMI, it is usually sufficient to minimize overshoot and undershoot, especially with signals leaving the circuit board.

The biggest problem with maintaining impedance control is the signal path discontinuities, including return path on ground plane:

1. The ideal signal path has a continuous copper plane immediately underneath. In such a case, impedance control is confined to proper terminations, usually at the load end. For slower signals, where EMI control is the predominant issue, source termination is often an appropriate choice, as it also limits the emission currents from leaving the driver chip. Source termination does slow the signal, which may not be acceptable for highest speeds.

2. The worst discontinuity occurs if the signal changes reference planes from a ground plane to a voltage plane, as illustrated in Figure 1. Clearly, ground to voltage vias can’t used to provide a return path, so the only option is to insert decoupling capacitors at the perimeter in order to provide a low impedance high frequency return path across the boundary. Unfortunately, this is not a fully acceptable solution at high frequencies, but will be reasonably good for lower frequency signal paths.

Figure 1: Return current path is discontinuous when switching reference planes

Figure 1: Return current path is discontinuous when switching reference planes

3. A lesser discontinuity occurs if the signal is transitioning from one ground plane to another. Here, the return path from plane to plane must be made continuous and impedance control effected. Typically, this is handled by inserting ground to ground vias around the perimeter of the signal via, and controlling the keepout, pad size and via size and length in order to match impedances.

4. The least problem of layer changing occurs when the signal transitions from one side of the ground plane to the other (see Figure 2). Since we haven’t changed reference planes, there is no issue with ground vias, so the impedance discontinuity is minimal. For highest speed signal integrity, you will need to minimize the impedance discontinuity by controlling the via size and length, and the diameter of the keepout.

Figure 2: Return current past discontinuity is minimized when keeping same reference plane

Figure 2: Return current past discontinuity is minimized when keeping same reference plane

5. Cuts in plane, as shown in Figure 3, shows a discontinuity in the signal return current path. The return path has to go around the gap in the plane, raising the characteristic impedance at the gap, and energizing the opening as a slot antenna. This can occur when a portion of the plane is stolen to accommodate another trace, at a split plane boundary, or at a connector cutout.

Figure 3: Signal return path is disrupted by cut in ground plane

Figure 3: Signal return path is disrupted by cut in ground plane

6. Signal path at mandatory discontinuities. This assumes that impedance control needs to be maintained across the boundary. Most notably, this will occur at the circuit board to connector boundary (see Figure 4), and is especially noticeable when the impedance of the cable doesn’t match the impedance at the circuit board. In such a case, an impedance matching network needs to be placed at the boundary. This is handled by controlling the copper parameters at the boundary. Larger cutouts increase inductance while leaving more copper at the boundary increases capacitance.

Figure 4: PCB to coax impedance matching

Figure 4: PCB to coax impedance matching

PCB Layout

For both EMI and signal integrity, good layout starts by identifying critical traces. In both cases, most of the problems lie with a very few of the traces. You don’t have the time or real estate to treat all the traces, so you concentrate on the few. But the critical traces are typically different for signal integrity and EMI.

For signal integrity, the problem is limited to the relatively few high speed signal traces. High speed serial data are the leader, and design will concentrate on the signal/return path and adjacent metallic members. For EMI, the problem concentrates on those lines entering or leaving the circuit board. The primary emitters are those that carry high speed clock and data lines, along with the parasitic coupling to slower lines, power lines and especially ground lines. The primary receptors are low level analog input lines for RFI and digital lines for transients.

Once these lines are identified, you can place the chips on board to facilitate good routing. The simpler the path for critical traces, the easier it is to maintain signal integrity and EMI control.


Starting with the supply voltages, the voltage tolerances are basically a signal integrity issue. This does not show up at the EMC level except to the extent that external interference corrupts voltage at the power supply or on-board regulators. The big difference lies with the demand for decoupling. Clock noise that shows up on the power rails and sneaks out the power cable will be an emission problem even if amplitudes are in the microvolt range, but won’t be a problem for signal integrity until it reaches the millivolt range. So decoupling demands for EMI are a thousand times more demanding than for signal integrity.

The chip manufacturer recommends decoupling capacitors as needed for Vcc droop. This means that the target frequencies for signal decoupling are at the clock frequency and below, while the frequencies for emissions are at the clock harmonics, typically ten times the clock frequency or even higher.

Thus, the demands for decoupling for emissions are substantially higher than with signal integrity. This doesn’t mean more capacitance, it means less inductance. At modern computer speeds, your high frequency harmonics are inevitably operating above the series resonant frequency of the typical decoupling capacitor. Just add one to two nanohenry of lead length in each decap and you will find that the impedance is too high for effective filtering. If the impedance is above one ohm, you should look for better filtering, or more decaps in parallel. The good news is that at higher frequencies, the interlayer capacitance of multilayer boards becomes the dominant factor above a couple hundred MHz.


Crosstalk can be an issue for both signal integrity and EMI. Crosstalk is unintended coupling to adjacent metallic members, usually to an adjacent signal, power or ground path.

Crosstalk includes field coupling from one line to an adjacent line. It is a major issue with cables that will usually need to be addressed, but may also be a problem with adjacent trace coupling at the circuit board level. Any coupling from very high speed signal lines can degrade signal quality (we see signal speeds well into the GHz range, and we hear 100 GHz is just around the corner), whether to an adjacent trace or any other metallic element on the circuit board. For EMI, crosstalk becomes a problem with I/O lines coupling energy to/from clock lines or sensitive on-board lines. Often, this problem can be eliminated by separating these lines. The spacing in between need not be wasted, but can be used for less critical lines. In both cases, increased spacing is beneficial, as coupling falls off with the square of the distance.

Other Signal Path Issues

In addition to crosstalk, other losses may come into play, with series resistance and shunt dielectric loses being the major issue.

Signal path losses would include series resistance in the conductive path and shunt conductance in the dielectric. For the most part, these losses are not a problem at the circuit board level, unless you are using a high resistance signal path, such as conductive epoxy (which is rarely used). These losses become much more of a problem at the cable level, especially with signal integrity, where losses track directly with eye diagram shrinkage, to the point of signal failure. For EMI, the problem is a bit less noticeable. But obviously, if the signal strength is weakened, it takes less external interference to create data errors.

Imbalance is an extension of crosstalk, becoming increasingly significant for differential signals as serial data speeds increase. Balance loss will occur with unequal coupling paths, as mentioned above, and will also show up due to unequal propagation times from driver to receiver. This is much more of an issue with signal integrity than with EMI.

Coupling to off-board elements is primarily an EMI issue, where coupling between elements on adjacent circuit boards may be significant. A typical case is where clock noise from a high speed microprocessor chip capacitively couples to an adjacent circuit board, then propagates to the outside world from there. A similar situation occurs if an internal cable is routed too close to this same chip. This situation is increasingly being handled by on-board chip shielding. This problem rarely occurs with signal integrity issues.

Analytical Software

Let’s take a look at analytical software, clearly, a topic of significant interest.

Any modeling that reduces hardware redesign effort is like money in the bank. So what is the status?

Our observation is the modeling for signal integrity is much more developed than for EMI. It is a much simpler task to model the signal path, with consideration limited to the signal path/return, plus coupling to adjacent metallic members. The EMI predictions are much more complex, as it involves consideration of many more circuit board coupling paths and common mode noise generation, both of which are difficult to identify, much less quantify. Additionally, calculations need to consider enclosure and cable shielding effectiveness, which involves identifying all the relevant parameters and quantifying them. In actuality, almost all of the modeling is directed at emissions. (We’ve seen almost nothing on modeling of immunity issues.) The bottom line is, consider yourself as doing well if your predictions are good within 20 dB, or a factor of 10. Well, that is better than nothing, but it still leaves a lot to be done by test and redesign.


Signal integrity has become an increasingly important part of EMI design. Good circuit board design is very important in both cases, but the emphasis is different. Most notably, signal integrity is primarily concerned with the critical high speed signal lines, and EMC is primarily concerned with the lines entering the circuit board.

Leave a Reply